The present invention relates to a semiconductor device or a ULSI composed of MOS transistors and, more particularly, to an integrated circuit device of high breakdown voltage, high speed and high density.
The density of the LSI such as the DRAM has advanced at a rate of four times every three years. The gate length of the MOS transistors composing the LSI has also gradually been micronized to less than 0.5 .mu.m at present. As this micronization advances, the problem of reliability is becoming serious. In order to solve this problem, the device structure is changing from the SD (Single Drain) through the DDD (Double Diffused Drain) to the LDD (Lightly Doped Drain). These techniques are disclosed in Japanese Patent Laid-Open No. 53-78181, for example. In accordance with these changes, the integrated circuit device of the prior art has its transistor structure replaced thoroughly.
As the field effect transistors of the prior art, on the other hand, there is a transistor which has an inverse-T gate electrode structure. This transistor is discussed in IEDM86, pp. 742, "A Novel Submicron LDD Transistor with Inverse-T Gate Structure".
In this prior art technique, the portion (which will be referred to the "side-wall gate") forming part of an inverse-T gate electrode and overhanging the lower side of the same gate electrode is thinned. This is because an ion implantation for source and drain formations is accomplished through that thin side-wall gate electrode.
Thus, the inverse-T side-wall gate is formed by not completely etching out but leaving the areas other than a gate pattern at the gate electrode etching step such as the reactive ion etching step in accordance with the above-specified report.
We have examined the prior art described above and have found the following problems.
The control of etching the side-wall gate is seriously difficult for the prior art. Specifically, only the control of etching will make it difficult to control the remaining thickness of the side-wall gate because of dispersions of the temperature, time and initial thickness. The lightly doped source and drain of the transistor having that structure are formed by the ion implantation through the thin gate electrode film overhanging in the inverse-T form. Unless the etching of the side-wall gate could then be controlled, there would arise a problem that the impurity profile of the lightly doped source and drain cannot be controlled.
The prior art described above is further followed by a problem that the electric resistance of the side-wall gate increases to delay gate line signals because the side-wall gate is thin.